1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and the semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) provided on a projecting semiconductor layer, and the semiconductor device.
2. Description of the Related Art
In the field of system large-scale integrated circuits (LSIs), to further enhance their performance, microfabrication of MOSFETs forming system LSIs is now being developed. In a fine MOSFET, unless the power supply voltage is low, the reliability of the MOSFET is reduced. However, when the power supply voltage is reduced, the current driving ability is reduced. To maintain the current driving ability, it is necessary to reduce the threshold voltage of the MOSFET in accordance with the reduction of the power supply voltage.
In general, when the threshold voltage is reduced, the off leakage current is increased and the gate length is reduced. In accordance with the reduction of the gate length, the short-channel effect is increased. Moreover, in accordance with the microfabrication of a MOSFET, a punch-through can easily occur between the source and drain regions of the MOSFET, thereby increasing the leakage current and degrading the cutoff characteristic.
As a MOSFET free from these problems, a fin MOSFET is known in which a projecting semiconductor layer (fin) is formed on a substrate and the opposite sides of the fin are used as channel.
In fin MOSFETs, fins are formed thin to enhance the characteristics. In these elements, the lower portion of each fin with no gate electrode thereon, which is close to the junction of each fin and substrate, is liable to be used as the current passage of a punch-through. Accordingly, it is important to suppress the forming of the punch-through.
It is desirable that fins should have an impurity profile in which the bottom portion has a high impurity concentration to suppress the leakage current, and the other portions, i.e., the channel region, contain a low concentration impurity to increase the degree of movement of carriers. It is also desirable that the substrate provided on the bottom of the fin has a low impurity concentration. This is because if the substrate has a high impurity concentration, the junction leakage current between the source/drain regions and the substrate is increased, thereby increasing the parasitic capacitance in accordance with an increase in the junction capacitance.
When impurity ions are implanted into a fin, they are implanted in a direction perpendicular to the substrate. If ions are implanted vertically, the probability of the ones of the implanted ions scattered to the ambient atmosphere being returned therefrom to the fin is low. Further, since no substances exist in the ambient atmosphere, the probability of the impurity ions scattered to the ambient atmosphere being implanted into the fin is low, too. Accordingly, the impurity concentration of the fin is inevitably lower than that of the flat portion.
Also, to make an arbitrary portion of the fin have a peak impurity concentration, impurity ions must be implanted into that portion by a high acceleration voltage. In this method, it is difficult to control the position in which the peak impurity concentration is detected, and only a gentle impurity profile is acquired.
Furthermore, it is possible to implantations into the substrate before forming the fin. In this case, however, the post process of forming the fin makes the impurity profile be gentle. Further, since ions are also implanted into the substrate, a high-impurity-concentration layer is formed in the substrate. Thus, this cannot impart an ideal concentration profile to the fin or substrate.
In addition, if two gate electrodes provided on the opposite sides of the fin are electrically disconnected from each other, the top of the fin may not be controlled by the gate electrodes, depending upon the positions of the electrodes. To avoid this, it is necessary to also form a punch-through stopper on the top of the fin. In the conventional manufacturing method, however, when a punch-through stopper is formed on the top of the fin, the impurity concentration of the channel region becomes high.
Concerning a technique related to a Fin FET, see Masaki et al., “A Fin FET Design Based on Three-Dimensional Process and Device Simulations”, Toshiba Corporation, IEEE, 2003.